A sample and hold circuit is used to sample a voltage, and retain it for some period of time. This is particularly useful in digital applications where a stable voltage is required in order to take accurate measurements. An Opamp follower on the input ensures that the circuit provides a low impedance copy of the input signal. The FET Q1 enables sampling; when the gate is high, current can flow to charge or discharge the capacitor C1, which serves to maintain the voltage while Q1 is off. Another opamp follower allows measurement of the voltage without discharging the capacitor in the process.
svg schematics by matt-chv is licensed under CC BY-SA 4.0
